JTAG Test Failed: Serial Bus Error

Hi,

Joint Test Action Group JTAG Test Access Port and Boundary-Scan Architecture.

It is a serial bus with four signals:

• TCK(Test Clock)
• TMS(Test Mode Select)
• TDI(Test Data Input)
• TDO(Test Data Output)

The bus is used as a test bus for the Boundary-Scan of ICs, as in Design-For-Testability.

For my official project, whenever I test the circuit with it, I got the following error.

JTAG test failed

Failed – TDO changes, but TDI pattern does not match.

Try the following hints to fix the problem:

• Try to use lower JTAG clock frequency.
• Do no0t use extra adapters, but use JTAGjet probe which matches your target connector.
• Make sure, that extra on-board buffer on JTAG lines are disabled (if possible)>
• Verify if pull-uppull-down resistors are in recommended range.
• Consult documentation (Help button) for more JTAG-problem solving hints.

I inspect every possible area where there might be a chance for error, but every thing is fine enough according to my technical knowledge.

I am therefore presenting this error to the experts here to guide me how to check and resolve this problem.

Thanks.