Information about Interrupts and registers

Information about Interrupts and registers

Hi Rizwan is here. The answer of you question is that The hardware and software designed for original PC communicated with the CPU by means of a hierarchical and predetermined set of signals calledinterrupts. When a device or a program needed some action on the part of the CPU it would signal this by sending an interrupt signal. The CPU would sort out the priority of the incoming interrupt requests, with lower number interrupts being handled first (it is common for the CPU to be handling several interrupts concurrently) and then locate the code associated with the interrupt (the Interrupt Request Handler) by examining the Interrupt Vector Table. Each interrupt (starting with interrupt 00H) is allocated four bytes in the vector table. These four bytes serve as an address pointer to the actual software routine associated with the interrupt. These routines may be stored in the ROM BIOS or more commonly in system RAM (where copies of ROM BIOS routines are often uploaded to provide faster access). The interrupt vector table is first initialized by the Start-up ROM but changes are made to it's contents as first the ROM Extensions and later the operating system files are loaded. The ability to update the contents of the interrupt vector table provides a means to easily expand operating system services by making a standard interrupt point to a new Interrupt Handler.

The other part of your question is One of a small number of high-speed memory locations in a computer's CPU. Registers differ from ordinary random access memory in several respects: There are only a small number of registers (the "register set"), typically 32 in a modern processorthough some, e.g. SPARC, have as many as 144. A register may be directly addressed with a few bits. In contrast, there are usually millions of words of main memory (RAM), requiring at least twenty bits to specify a memory location. Main memory locations are often specified indirectly, using an {indirect addressing} mode where the actual memory address is held in a register. Registers are fast; typically, two registers can be read and a third written — all in a single cycle. Memory is slower; a single access can require several cycles.